The present invention relates to an operational amplifier, and more particularly, to an operational amplifier capable of reducing power consumption. Further, the present invention relates to a cascode operational amp which consumes a small amount of current.
The operational amplifier (OP amp) has been widely used in an analog applications. A general operational amplifier is designed on the basis of a two-stage differential amplifier. In a general two-stage differential amplifier, gain is high, but the frequency characteristics are degraded. In order to improve frequency characteristics, a folded cascode OP amp is often used. However, while the cascode OP amp has relatively good frequency characteristics, it suffers the disadvantage of high current consumption.
FIG. 1 is a circuit diagram of a conventional OP amp 1. In FIG. 1, the structure of the OP amp 1 is functionally divided into an input portion 10, a bias portion 20, an amplifying portion 30 and an outputting portion 40. The bias portion 20 provides a bias necessary for operating the input portion 10, the amplifying portion 30 and the outputting portion 40. The amplifying portion 30 amplifies signals ni and pi which are input from external sources.
The bias portion 20 is connected to a power supply VDDA through its source, and has a structure made up of a series connection of a first PMOS transistor 22 whose gate and drain are connected, a resistor 24, and a first NMOS transistor 26 whose gate and drain are connected and whose source is connected to a ground voltage VSSA. The first PMOS and NMOS transistors 22 and 26 act as a forward diode with respect to the VDDA.
The input portion 10 includes second NMOS and PMOS transistors 11 and 15 connected to a first input signal ni through their gates, third NMOS and PMOS transistors 12 and 16 connected to a second input signal pi through their gates, a fourth NMOS transistor 13 whose drain is commonly connected to the sources of the second and third NMOS transistors 11 and 12, whose gate is connected to that of the first NMOS transistor 26, and whose source is connected to the VSSA, and a fourth PMOS transistor 17 whose drain is commonly connected to the sources of the second and third PMOS transistors 15 and 16, whose gate is connected to that of the first PMOS transistor 22, and whose source is connected to the VDDA.
The amplifying portion 30 includes a fifth PMOS transistor 32 whose source is connected to the VDDA and whose gate is connected to that of the first PMOS transistor 22, a sixth PMOS transistor 34 whose source is connected to the drain of the fifth PMOS transistor 32 and whose gate and drain are connected to each other, a fifth NMOS transistor 36 whose drain and gate are connected to the drain of the sixth PMOS transistor 34, and a sixth NMOS transistor 38 whose drain is connected to the source of the fifth NMOS transistor 36, whose gate is connected to that of the first NMOS transistor 26, and whose source is connected to the VSSA.
The output portion 40 includes a seventh PMOS transistor 42 whose source is connected to the VDDA and whose gate is connected to that of the first PMOS transistor 22, an eighth transistor PMOS 44 whose source is connected to the drain of the seventh PMOS transistor 42 and whose gate is connected to that of the sixth PMOS transistor 34, a seventh NMOS transistor 46 whose drain is connected to the drain of the eighth PMOS transistor 44 and whose gate is connected to the gate of the fifth NMOS transistor 36, and an eighth NMOS transistor 48 whose drain is connected to the source of the seventh NMOS transistor 46, whose gate is connected to that of the first NMOS transistor 26, and whose source is connected to the VSSA. The eighth PMOS transistor 44 outputs an output signal Vout through its drain.
The amplifying portion 30 and the output portion 40 are symmetrical with each other in that a one-to-one ratio of elements exists. That is, the fifth and seventh PMOS transistors 32 and 42, the sixth and eighth PMOS transistors 34 and 44, the fifth and seventh NMOS transistors 36 and 46, and the sixth and eighth NMOS transistors 38 and 48 are symmetrically connected to each other. Thus, the amplifying portion 30 and the output portion 40 the are the same with respect to the flow of current. In order to improve the gain and the frequency characteristics of the OP amp 1, a large amount of current should flow in the output portion 40. Accordingly, a large amount of current also flows in the amplifying portion 30. However, in an actual case, since only the current flowing in the output portion 40 is necessary to control an output signal of the OP amp 1, the flow of much current in the amplifying portion 30 results in the unnecessary consumption of current. Such an OP amp 1 is not appropriate for pursuing low-power consuming products.
In the conventional OP amp 1 described above, there exists a drawback in that substantial current flows in the amplifying portion 30 such that a large amount of power is consumed thereby.